Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
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software_version_and_target_device
date_generatedFri Jun 05 14:53:37 2015 product_versionVivado v2015.1 (64-bit)
build_version1215546 os_platformWIN64
registration_id1_2_4_3 tool_flowVivado
betaFALSE route_designTRUE
target_familyzynq target_devicexc7z010
target_packageclg400 target_speed-2
random_idee6da61c7d7855f4a84003a5de88b917 project_id1296bc365dd4435082fc767027fdc082
project_iteration0

user_environment
os_nameMicrosoft Windows 7 , 64-bit os_releaseService Pack 1 (build 7601)
cpu_nameIntel(R) Core(TM) i7-3740QM CPU @ 2.70GHz cpu_speed2691 MHz
total_processors1 system_ram34.000 GB

vivado_usage
project_data
srcsetcount=5 constraintsetcount=2 designmode=RTL prproject=false
reconfigpartitioncount=0 reconfigmodulecount=0 hdproject=false partitioncount=0
synthesisstrategy=Vivado Synthesis Defaults implstrategy=Vivado Implementation Defaults currentsynthesisrun=synth_1 currentimplrun=impl_1
totalsynthesisruns=1 totalimplruns=1

unisim_transformation
pre_unisim_transformation
bibuf=130 bufg=10 carry4=110 fdre=4188
fdse=173 gnd=143 ibuf=5 iobuf=13
lut1=754 lut2=158 lut3=886 lut4=342
lut5=445 lut6=1503 muxf7=129 obuf=51
ps7=1 ramb36e1=42 srl16e=33 srlc32e=105
vcc=124
post_unisim_transformation
bibuf=130 bufg=10 carry4=110 fdre=4188
fdse=173 gnd=143 ibuf=18 lut1=754
lut2=158 lut3=886 lut4=342 lut5=445
lut6=1503 muxf7=129 obuf=51 obuft=13
ps7=1 ramb36e1=42 srl16e=33 srlc32e=105
vcc=124

placer
usage
lut=2913 ff=3378 bram36=42 bram18=0
ctrls=114 dsp=0 iob=69 bufg=0
global_clocks=3 pll=0 bufr=0 nets=13427
movable_instances=7488 pins=51587 bogomips=0 effort=2
threads=2 placer_timing_driven=1 timing_constraints_exist=1 placer_runtime=12.778000

power_opt_design
usage
slice_registers_augmented=0 slice_registers_newly_gated=0 slice_registers_total=3378 srls_augmented=0
srls_newly_gated=0 srls_total=138 bram_ports_augmented=32 bram_ports_newly_gated=0
bram_ports_total=84 flow_state=default
command_line_options_spo
-clocks=default::[not_specified] -include_cells=default::[not_specified] -exclude_cells=default::[not_specified] -cell_types=default::all

ip_statistics
IP_Integrator/1
iptotal=1 x_ipproduct=Vivado 2015.1 x_ipvendor=xilinx.com x_iplibrary=BlockDiagram
x_ipname=base x_ipversion=1.00.a x_iplanguage=VERILOG numblks=20
numreposblks=14 numnonxlnxblks=1 numhierblks=6 maxhierdepth=0
da_axi4_cnt=2 da_bram_cntlr_cnt=3 synth_mode=Global
axi_bram_ctrl/1
iptotal=1 x_ipproduct=Vivado 2015.1 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=axi_bram_ctrl x_ipversion=4.0 x_ipcorerevision=4 x_iplanguage=VERILOG
x_ipsimlanguage=MIXED c_bram_inst_mode=EXTERNAL c_memory_depth=2048 c_bram_addr_width=11
c_s_axi_addr_width=13 c_s_axi_data_width=32 c_s_axi_id_width=1 c_s_axi_protocol=AXI4LITE
c_s_axi_supports_narrow_burst=0 c_single_port_bram=1 c_family=zynq c_s_axi_ctrl_addr_width=32
c_s_axi_ctrl_data_width=32 c_ecc=0 c_ecc_type=0 c_fault_inject=0
c_ecc_onoff_reset_value=0
axi_bram_ctrl/2
iptotal=1 x_ipproduct=Vivado 2015.1 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=axi_bram_ctrl x_ipversion=4.0 x_ipcorerevision=4 x_iplanguage=VERILOG
x_ipsimlanguage=MIXED c_bram_inst_mode=EXTERNAL c_memory_depth=2048 c_bram_addr_width=11
c_s_axi_addr_width=13 c_s_axi_data_width=32 c_s_axi_id_width=1 c_s_axi_protocol=AXI4LITE
c_s_axi_supports_narrow_burst=0 c_single_port_bram=1 c_family=zynq c_s_axi_ctrl_addr_width=32
c_s_axi_ctrl_data_width=32 c_ecc=0 c_ecc_type=0 c_fault_inject=0
c_ecc_onoff_reset_value=0
axi_bram_ctrl/3
iptotal=1 x_ipproduct=Vivado 2015.1 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=axi_bram_ctrl x_ipversion=4.0 x_ipcorerevision=4 x_iplanguage=VERILOG
x_ipsimlanguage=MIXED c_bram_inst_mode=EXTERNAL c_memory_depth=32768 c_bram_addr_width=15
c_s_axi_addr_width=17 c_s_axi_data_width=32 c_s_axi_id_width=1 c_s_axi_protocol=AXI4
c_s_axi_supports_narrow_burst=0 c_single_port_bram=0 c_family=zynq c_s_axi_ctrl_addr_width=32
c_s_axi_ctrl_data_width=32 c_ecc=0 c_ecc_type=0 c_fault_inject=0
c_ecc_onoff_reset_value=0
axi_crossbar_v2_1_axi_crossbar/1
iptotal=1 x_ipproduct=Vivado 2015.1 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=axi_crossbar x_ipversion=2.1 x_ipcorerevision=6 x_iplanguage=VERILOG
x_ipsimlanguage=MIXED c_family=zynq c_num_slave_slots=1 c_num_master_slots=4
c_axi_id_width=12 c_axi_addr_width=32 c_axi_data_width=32 c_axi_protocol=0
c_num_addr_ranges=1 c_m_axi_base_addr=0x0000000042000000000000004001000000000000400000000000000043c00000 c_m_axi_addr_width=0x000000110000000d0000000d00000010 c_s_axi_base_id=0x00000000
c_s_axi_thread_id_width=0x0000000c c_axi_supports_user_signals=0 c_axi_awuser_width=1 c_axi_aruser_width=1
c_axi_wuser_width=1 c_axi_ruser_width=1 c_axi_buser_width=1 c_m_axi_write_connectivity=0x00000001000000010000000100000001
c_m_axi_read_connectivity=0x00000001000000010000000100000001 c_r_register=1 c_s_axi_single_thread=0x00000001 c_s_axi_write_acceptance=0x00000001
c_s_axi_read_acceptance=0x00000001 c_m_axi_write_issuing=0x00000001000000010000000100000001 c_m_axi_read_issuing=0x00000001000000010000000100000001 c_s_axi_arb_priority=0x00000000
c_m_axi_secure=0x00000000000000000000000000000000 c_connectivity_mode=0
axi_protocol_converter_v2_1_axi_protocol_converter/1
iptotal=1 x_ipproduct=Vivado 2015.1 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=axi_protocol_converter x_ipversion=2.1 x_ipcorerevision=5 x_iplanguage=VERILOG
x_ipsimlanguage=MIXED c_family=zynq c_m_axi_protocol=2 c_s_axi_protocol=0
c_ignore_id=1 c_axi_id_width=1 c_axi_addr_width=32 c_axi_data_width=32
c_axi_supports_write=1 c_axi_supports_read=1 c_axi_supports_user_signals=0 c_axi_awuser_width=1
c_axi_aruser_width=1 c_axi_wuser_width=1 c_axi_ruser_width=1 c_axi_buser_width=1
c_translation_mode=2
axi_protocol_converter_v2_1_axi_protocol_converter/2
iptotal=1 x_ipproduct=Vivado 2015.1 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=axi_protocol_converter x_ipversion=2.1 x_ipcorerevision=5 x_iplanguage=VERILOG
x_ipsimlanguage=MIXED c_family=zynq c_m_axi_protocol=2 c_s_axi_protocol=0
c_ignore_id=1 c_axi_id_width=1 c_axi_addr_width=32 c_axi_data_width=32
c_axi_supports_write=1 c_axi_supports_read=1 c_axi_supports_user_signals=0 c_axi_awuser_width=1
c_axi_aruser_width=1 c_axi_wuser_width=1 c_axi_ruser_width=1 c_axi_buser_width=1
c_translation_mode=2
axi_protocol_converter_v2_1_axi_protocol_converter/3
iptotal=1 x_ipproduct=Vivado 2015.1 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=axi_protocol_converter x_ipversion=2.1 x_ipcorerevision=5 x_iplanguage=VERILOG
x_ipsimlanguage=MIXED c_family=zynq c_m_axi_protocol=2 c_s_axi_protocol=0
c_ignore_id=1 c_axi_id_width=1 c_axi_addr_width=32 c_axi_data_width=32
c_axi_supports_write=1 c_axi_supports_read=1 c_axi_supports_user_signals=0 c_axi_awuser_width=1
c_axi_aruser_width=1 c_axi_wuser_width=1 c_axi_ruser_width=1 c_axi_buser_width=1
c_translation_mode=2
axi_protocol_converter_v2_1_axi_protocol_converter/4
iptotal=1 x_ipproduct=Vivado 2015.1 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=axi_protocol_converter x_ipversion=2.1 x_ipcorerevision=5 x_iplanguage=VERILOG
x_ipsimlanguage=MIXED c_family=zynq c_m_axi_protocol=0 c_s_axi_protocol=1
c_ignore_id=0 c_axi_id_width=12 c_axi_addr_width=32 c_axi_data_width=32
c_axi_supports_write=1 c_axi_supports_read=1 c_axi_supports_user_signals=0 c_axi_awuser_width=1
c_axi_aruser_width=1 c_axi_wuser_width=1 c_axi_ruser_width=1 c_axi_buser_width=1
c_translation_mode=2
blk_mem_gen_v8_2/1
iptotal=1 x_ipproduct=Vivado 2015.1 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=blk_mem_gen x_ipversion=8.2 x_ipcorerevision=5 x_iplanguage=VERILOG
x_ipsimlanguage=MIXED c_family=zynq c_xdevicefamily=zynq c_elaboration_dir=./
c_interface_type=0 c_axi_type=1 c_axi_slave_type=0 c_use_bram_block=1
c_enable_32bit_address=1 c_ctrl_ecc_algo=NONE c_has_axi_id=0 c_axi_id_width=4
c_mem_type=2 c_byte_size=8 c_algorithm=1 c_prim_type=1
c_load_init_file=0 c_init_file_name=no_coe_file_loaded c_init_file=NONE c_use_default_data=0
c_default_data=0 c_has_rsta=1 c_rst_priority_a=CE c_rstram_a=0
c_inita_val=0 c_has_ena=1 c_has_regcea=0 c_use_byte_wea=1
c_wea_width=4 c_write_mode_a=WRITE_FIRST c_write_width_a=32 c_read_width_a=32
c_write_depth_a=8192 c_read_depth_a=8192 c_addra_width=32 c_has_rstb=1
c_rst_priority_b=CE c_rstram_b=0 c_initb_val=0 c_has_enb=1
c_has_regceb=0 c_use_byte_web=1 c_web_width=4 c_write_mode_b=WRITE_FIRST
c_write_width_b=32 c_read_width_b=32 c_write_depth_b=8192 c_read_depth_b=8192
c_addrb_width=32 c_has_mem_output_regs_a=0 c_has_mem_output_regs_b=0 c_has_mux_output_regs_a=0
c_has_mux_output_regs_b=0 c_mux_pipeline_stages=0 c_has_softecc_input_regs_a=0 c_has_softecc_output_regs_b=0
c_use_softecc=0 c_use_ecc=0 c_en_ecc_pipe=0 c_has_injecterr=0
c_sim_collision_check=ALL c_common_clk=0 c_disable_warn_bhv_coll=0 c_en_sleep_pin=0
c_use_uram=0 c_en_rdaddra_chg=0 c_en_rdaddrb_chg=0 c_en_deepsleep_pin=0
c_en_shutdown_pin=0 c_disable_warn_bhv_range=0 c_count_36k_bram=8 c_count_18k_bram=0
c_est_power_summary=Estimated Power for IP _ 20.388 mW
blk_mem_gen_v8_2/2
iptotal=1 x_ipproduct=Vivado 2015.1 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=blk_mem_gen x_ipversion=8.2 x_ipcorerevision=5 x_iplanguage=VERILOG
x_ipsimlanguage=MIXED c_family=zynq c_xdevicefamily=zynq c_elaboration_dir=./
c_interface_type=0 c_axi_type=1 c_axi_slave_type=0 c_use_bram_block=1
c_enable_32bit_address=1 c_ctrl_ecc_algo=NONE c_has_axi_id=0 c_axi_id_width=4
c_mem_type=2 c_byte_size=8 c_algorithm=1 c_prim_type=1
c_load_init_file=0 c_init_file_name=no_coe_file_loaded c_init_file=NONE c_use_default_data=0
c_default_data=0 c_has_rsta=1 c_rst_priority_a=CE c_rstram_a=0
c_inita_val=0 c_has_ena=1 c_has_regcea=0 c_use_byte_wea=1
c_wea_width=4 c_write_mode_a=WRITE_FIRST c_write_width_a=32 c_read_width_a=32
c_write_depth_a=2048 c_read_depth_a=2048 c_addra_width=32 c_has_rstb=1
c_rst_priority_b=CE c_rstram_b=0 c_initb_val=0 c_has_enb=1
c_has_regceb=0 c_use_byte_web=1 c_web_width=4 c_write_mode_b=WRITE_FIRST
c_write_width_b=32 c_read_width_b=32 c_write_depth_b=2048 c_read_depth_b=2048
c_addrb_width=32 c_has_mem_output_regs_a=0 c_has_mem_output_regs_b=0 c_has_mux_output_regs_a=0
c_has_mux_output_regs_b=0 c_mux_pipeline_stages=0 c_has_softecc_input_regs_a=0 c_has_softecc_output_regs_b=0
c_use_softecc=0 c_use_ecc=0 c_en_ecc_pipe=0 c_has_injecterr=0
c_sim_collision_check=ALL c_common_clk=0 c_disable_warn_bhv_coll=0 c_en_sleep_pin=0
c_use_uram=0 c_en_rdaddra_chg=0 c_en_rdaddrb_chg=0 c_en_deepsleep_pin=0
c_en_shutdown_pin=0 c_disable_warn_bhv_range=0 c_count_36k_bram=2 c_count_18k_bram=0
c_est_power_summary=Estimated Power for IP _ 10.7492 mW
blk_mem_gen_v8_2/3
iptotal=1 x_ipproduct=Vivado 2015.1 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=blk_mem_gen x_ipversion=8.2 x_ipcorerevision=5 x_iplanguage=VERILOG
x_ipsimlanguage=MIXED c_family=zynq c_xdevicefamily=zynq c_elaboration_dir=./
c_interface_type=0 c_axi_type=1 c_axi_slave_type=0 c_use_bram_block=1
c_enable_32bit_address=1 c_ctrl_ecc_algo=NONE c_has_axi_id=0 c_axi_id_width=4
c_mem_type=2 c_byte_size=8 c_algorithm=1 c_prim_type=1
c_load_init_file=0 c_init_file_name=no_coe_file_loaded c_init_file=NONE c_use_default_data=0
c_default_data=0 c_has_rsta=1 c_rst_priority_a=CE c_rstram_a=0
c_inita_val=0 c_has_ena=1 c_has_regcea=0 c_use_byte_wea=1
c_wea_width=4 c_write_mode_a=WRITE_FIRST c_write_width_a=32 c_read_width_a=32
c_write_depth_a=32768 c_read_depth_a=32768 c_addra_width=32 c_has_rstb=1
c_rst_priority_b=CE c_rstram_b=0 c_initb_val=0 c_has_enb=1
c_has_regceb=0 c_use_byte_web=1 c_web_width=4 c_write_mode_b=WRITE_FIRST
c_write_width_b=32 c_read_width_b=32 c_write_depth_b=32768 c_read_depth_b=32768
c_addrb_width=32 c_has_mem_output_regs_a=0 c_has_mem_output_regs_b=0 c_has_mux_output_regs_a=0
c_has_mux_output_regs_b=0 c_mux_pipeline_stages=0 c_has_softecc_input_regs_a=0 c_has_softecc_output_regs_b=0
c_use_softecc=0 c_use_ecc=0 c_en_ecc_pipe=0 c_has_injecterr=0
c_sim_collision_check=ALL c_common_clk=0 c_disable_warn_bhv_coll=0 c_en_sleep_pin=0
c_use_uram=0 c_en_rdaddra_chg=0 c_en_rdaddrb_chg=0 c_en_deepsleep_pin=0
c_en_shutdown_pin=0 c_disable_warn_bhv_range=0 c_count_36k_bram=32 c_count_18k_bram=0
c_est_power_summary=Estimated Power for IP _ 20.388 mW
proc_sys_reset/1
iptotal=1 x_ipproduct=Vivado 2015.1 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=proc_sys_reset x_ipversion=5.0 x_ipcorerevision=7 x_iplanguage=VERILOG
x_ipsimlanguage=MIXED c_family=zynq c_ext_rst_width=4 c_aux_rst_width=4
c_ext_reset_high=0 c_aux_reset_high=0 c_num_bus_rst=1 c_num_perp_rst=1
c_num_interconnect_aresetn=1 c_num_perp_aresetn=1
processing_system7_v5.5_user_configuration/1
iptotal=1 pcw_uiparam_ddr_freq_mhz=533.333333 pcw_uiparam_ddr_bank_addr_count=3 pcw_uiparam_ddr_row_addr_count=14
pcw_uiparam_ddr_col_addr_count=10 pcw_uiparam_ddr_cl=7 pcw_uiparam_ddr_cwl=6 pcw_uiparam_ddr_t_rcd=7
pcw_uiparam_ddr_t_rp=7 pcw_uiparam_ddr_t_rc=48.75 pcw_uiparam_ddr_t_ras_min=35.0 pcw_uiparam_ddr_t_faw=30.0
pcw_uiparam_ddr_al=0 pcw_uiparam_ddr_dqs_to_clk_delay_0=0.0 pcw_uiparam_ddr_dqs_to_clk_delay_1=0.0 pcw_uiparam_ddr_dqs_to_clk_delay_2=0.0
pcw_uiparam_ddr_dqs_to_clk_delay_3=0.0 pcw_uiparam_ddr_board_delay0=0.0 pcw_uiparam_ddr_board_delay1=0.0 pcw_uiparam_ddr_board_delay2=0.0
pcw_uiparam_ddr_board_delay3=0.0 pcw_uiparam_ddr_dqs_0_length_mm=0 pcw_uiparam_ddr_dqs_1_length_mm=0 pcw_uiparam_ddr_dqs_2_length_mm=0
pcw_uiparam_ddr_dqs_3_length_mm=0 pcw_uiparam_ddr_dq_0_length_mm=0 pcw_uiparam_ddr_dq_1_length_mm=0 pcw_uiparam_ddr_dq_2_length_mm=0
pcw_uiparam_ddr_dq_3_length_mm=0 pcw_uiparam_ddr_clock_0_length_mm=0 pcw_uiparam_ddr_clock_1_length_mm=0 pcw_uiparam_ddr_clock_2_length_mm=0
pcw_uiparam_ddr_clock_3_length_mm=0 pcw_uiparam_ddr_dqs_0_package_length=101.239 pcw_uiparam_ddr_dqs_1_package_length=79.5025 pcw_uiparam_ddr_dqs_2_package_length=60.536
pcw_uiparam_ddr_dqs_3_package_length=71.7715 pcw_uiparam_ddr_dq_0_package_length=104.5365 pcw_uiparam_ddr_dq_1_package_length=70.676 pcw_uiparam_ddr_dq_2_package_length=59.1615
pcw_uiparam_ddr_dq_3_package_length=81.319 pcw_uiparam_ddr_clock_0_package_length=54.563 pcw_uiparam_ddr_clock_1_package_length=54.563 pcw_uiparam_ddr_clock_2_package_length=54.563
pcw_uiparam_ddr_clock_3_package_length=54.563 pcw_uiparam_ddr_dqs_0_propogation_delay=160 pcw_uiparam_ddr_dqs_1_propogation_delay=160 pcw_uiparam_ddr_dqs_2_propogation_delay=160
pcw_uiparam_ddr_dqs_3_propogation_delay=160 pcw_uiparam_ddr_dq_0_propogation_delay=160 pcw_uiparam_ddr_dq_1_propogation_delay=160 pcw_uiparam_ddr_dq_2_propogation_delay=160
pcw_uiparam_ddr_dq_3_propogation_delay=160 pcw_uiparam_ddr_clock_0_propogation_delay=160 pcw_uiparam_ddr_clock_1_propogation_delay=160 pcw_uiparam_ddr_clock_2_propogation_delay=160
pcw_uiparam_ddr_clock_3_propogation_delay=160 pcw_crystal_peripheral_freqmhz=33.333333 pcw_apu_peripheral_freqmhz=666.666666 pcw_dci_peripheral_freqmhz=10.159
pcw_qspi_peripheral_freqmhz=200 pcw_smc_peripheral_freqmhz=100 pcw_usb0_peripheral_freqmhz=60 pcw_usb1_peripheral_freqmhz=60
pcw_sdio_peripheral_freqmhz=100 pcw_uart_peripheral_freqmhz=100 pcw_spi_peripheral_freqmhz=166.666666 pcw_can_peripheral_freqmhz=100
pcw_can0_peripheral_freqmhz=-1 pcw_can1_peripheral_freqmhz=-1 pcw_wdt_peripheral_freqmhz=133.333333 pcw_ttc_peripheral_freqmhz=50
pcw_ttc0_clk0_peripheral_freqmhz=133.333333 pcw_ttc0_clk1_peripheral_freqmhz=133.333333 pcw_ttc0_clk2_peripheral_freqmhz=133.333333 pcw_ttc1_clk0_peripheral_freqmhz=133.333333
pcw_ttc1_clk1_peripheral_freqmhz=133.333333 pcw_ttc1_clk2_peripheral_freqmhz=133.333333 pcw_pcap_peripheral_freqmhz=200 pcw_tpiu_peripheral_freqmhz=200
pcw_fpga0_peripheral_freqmhz=40 pcw_fpga1_peripheral_freqmhz=50 pcw_fpga2_peripheral_freqmhz=60 pcw_fpga3_peripheral_freqmhz=2
pcw_override_basic_clock=0 pcw_armpll_ctrl_fbdiv=40 pcw_iopll_ctrl_fbdiv=54 pcw_ddrpll_ctrl_fbdiv=32
pcw_cpu_cpu_pll_freqmhz=1333.333 pcw_io_io_pll_freqmhz=1800.000 pcw_ddr_ddr_pll_freqmhz=1066.667 pcw_use_m_axi_gp0=1
pcw_use_m_axi_gp1=0 pcw_use_s_axi_gp0=0 pcw_use_s_axi_gp1=0 pcw_use_s_axi_acp=0
pcw_use_s_axi_hp0=0 pcw_use_s_axi_hp1=0 pcw_use_s_axi_hp2=0 pcw_use_s_axi_hp3=0
pcw_m_axi_gp0_freqmhz=40 pcw_m_axi_gp1_freqmhz=10 pcw_s_axi_gp0_freqmhz=10 pcw_s_axi_gp1_freqmhz=10
pcw_s_axi_acp_freqmhz=10 pcw_s_axi_hp0_freqmhz=10 pcw_s_axi_hp1_freqmhz=10 pcw_s_axi_hp2_freqmhz=10
pcw_s_axi_hp3_freqmhz=10 pcw_use_cross_trigger=0 pcw_ftm_cti_in0=DISABLED pcw_ftm_cti_in1=DISABLED
pcw_ftm_cti_in2=DISABLED pcw_ftm_cti_in3=DISABLED pcw_ftm_cti_out0=DISABLED pcw_ftm_cti_out1=DISABLED
pcw_ftm_cti_out2=DISABLED pcw_ftm_cti_out3=DISABLED pcw_uart0_baud_rate=115200 pcw_uart1_baud_rate=115200
pcw_s_axi_hp0_data_width=64 pcw_s_axi_hp1_data_width=64 pcw_s_axi_hp2_data_width=64 pcw_s_axi_hp3_data_width=64
pcw_irq_f2p_mode=DIRECT pcw_preset_bank0_voltage=LVCMOS 3.3V pcw_preset_bank1_voltage=LVCMOS 3.3V pcw_uiparam_ddr_enable=1
pcw_uiparam_ddr_adv_enable=0 pcw_uiparam_ddr_memory_type=DDR 3 pcw_uiparam_ddr_ecc=Disabled pcw_uiparam_ddr_bus_width=32 Bit
pcw_uiparam_ddr_bl=8 pcw_uiparam_ddr_high_temp=Normal (0-85) pcw_uiparam_ddr_partno=MT41J128M8 JP-125 pcw_uiparam_ddr_dram_width=8 Bits
pcw_uiparam_ddr_device_capacity=1024 MBits pcw_uiparam_ddr_speed_bin=DDR3_1066F pcw_uiparam_ddr_train_write_level=1 pcw_uiparam_ddr_train_read_gate=1
pcw_uiparam_ddr_train_data_eye=1 pcw_uiparam_ddr_clock_stop_en=0 pcw_uiparam_ddr_use_internal_vref=0 pcw_ddr_port0_hpr_enable=0
pcw_ddr_port1_hpr_enable=0 pcw_ddr_port2_hpr_enable=0 pcw_ddr_port3_hpr_enable=0 pcw_ddr_hprlpr_queue_partition=HPR(0)/LPR(32)
pcw_ddr_lpr_to_critical_priority_level=2 pcw_ddr_hpr_to_critical_priority_level=15 pcw_ddr_write_to_critical_priority_level=2 pcw_nand_peripheral_enable=0
pcw_nand_grp_d8_enable=0 pcw_nor_peripheral_enable=0 pcw_nor_grp_a25_enable=0 pcw_nor_grp_cs0_enable=0
pcw_nor_grp_sram_cs0_enable=0 pcw_nor_grp_cs1_enable=0 pcw_nor_grp_sram_cs1_enable=0 pcw_nor_grp_sram_int_enable=0
pcw_qspi_peripheral_enable=1 pcw_qspi_qspi_io=MIO 1 .. 6 pcw_qspi_grp_single_ss_enable=1 pcw_qspi_grp_single_ss_io=MIO 1 .. 6
pcw_qspi_grp_ss1_enable=0 pcw_qspi_grp_io1_enable=0 pcw_qspi_grp_fbclk_enable=1 pcw_qspi_grp_fbclk_io=MIO 8
pcw_qspi_internal_highaddress=0xFCFFFFFF pcw_enet0_peripheral_enable=0 pcw_enet0_grp_mdio_enable=0 pcw_enet0_reset_enable=0
pcw_enet1_peripheral_enable=0 pcw_enet1_grp_mdio_enable=0 pcw_enet1_reset_enable=0 pcw_sd0_peripheral_enable=0
pcw_sd0_grp_cd_enable=0 pcw_sd0_grp_wp_enable=0 pcw_sd0_grp_pow_enable=0 pcw_sd1_peripheral_enable=0
pcw_sd1_grp_cd_enable=0 pcw_sd1_grp_wp_enable=0 pcw_sd1_grp_pow_enable=0 pcw_uart0_peripheral_enable=1
pcw_uart0_uart0_io=MIO 22 .. 23 pcw_uart0_grp_full_enable=0 pcw_uart1_peripheral_enable=1 pcw_uart1_uart1_io=MIO 48 .. 49
pcw_uart1_grp_full_enable=0 pcw_spi0_peripheral_enable=1 pcw_spi0_spi0_io=MIO 16 .. 21 pcw_spi0_grp_ss0_enable=1
pcw_spi0_grp_ss0_io=MIO 18 pcw_spi0_grp_ss1_enable=1 pcw_spi0_grp_ss1_io=MIO 19 pcw_spi0_grp_ss2_enable=1
pcw_spi0_grp_ss2_io=MIO 20 pcw_spi1_peripheral_enable=0 pcw_spi1_grp_ss0_enable=0 pcw_spi1_grp_ss1_enable=0
pcw_spi1_grp_ss2_enable=0 pcw_can0_peripheral_enable=0 pcw_can0_grp_clk_enable=0 pcw_can1_peripheral_enable=0
pcw_can1_grp_clk_enable=0 pcw_trace_peripheral_enable=0 pcw_trace_grp_2bit_enable=0 pcw_trace_grp_4bit_enable=0
pcw_trace_grp_8bit_enable=0 pcw_trace_grp_16bit_enable=0 pcw_trace_grp_32bit_enable=0 pcw_wdt_peripheral_enable=0
pcw_ttc0_peripheral_enable=1 pcw_ttc0_ttc0_io=EMIO pcw_ttc1_peripheral_enable=0 pcw_pjtag_peripheral_enable=0
pcw_usb0_peripheral_enable=0 pcw_usb0_reset_enable=0 pcw_usb1_peripheral_enable=0 pcw_usb1_reset_enable=0
pcw_i2c0_peripheral_enable=1 pcw_i2c0_i2c0_io=MIO 14 .. 15 pcw_i2c0_grp_int_enable=1 pcw_i2c0_grp_int_io=EMIO
pcw_i2c0_reset_enable=0 pcw_i2c1_peripheral_enable=1 pcw_i2c1_i2c1_io=MIO 12 .. 13 pcw_i2c1_grp_int_enable=1
pcw_i2c1_grp_int_io=EMIO pcw_i2c1_reset_enable=0 pcw_gpio_peripheral_enable=0 pcw_gpio_mio_gpio_enable=1
pcw_gpio_mio_gpio_io=MIO pcw_gpio_emio_gpio_enable=0 pcw_apu_clk_ratio_enable=6:2:1 pcw_enet0_peripheral_freqmhz=1000 Mbps
pcw_enet1_peripheral_freqmhz=1000 Mbps pcw_cpu_peripheral_clksrc=ARM PLL pcw_ddr_peripheral_clksrc=DDR PLL pcw_smc_peripheral_clksrc=IO PLL
pcw_qspi_peripheral_clksrc=IO PLL pcw_sdio_peripheral_clksrc=IO PLL pcw_uart_peripheral_clksrc=IO PLL pcw_spi_peripheral_clksrc=IO PLL
pcw_can_peripheral_clksrc=IO PLL pcw_fclk0_peripheral_clksrc=IO PLL pcw_fclk1_peripheral_clksrc=IO PLL pcw_fclk2_peripheral_clksrc=IO PLL
pcw_fclk3_peripheral_clksrc=IO PLL pcw_enet0_peripheral_clksrc=IO PLL pcw_enet1_peripheral_clksrc=IO PLL pcw_can0_peripheral_clksrc=External
pcw_can1_peripheral_clksrc=External pcw_tpiu_peripheral_clksrc=External pcw_ttc0_clk0_peripheral_clksrc=CPU_1X pcw_ttc0_clk1_peripheral_clksrc=CPU_1X
pcw_ttc0_clk2_peripheral_clksrc=CPU_1X pcw_ttc1_clk0_peripheral_clksrc=CPU_1X pcw_ttc1_clk1_peripheral_clksrc=CPU_1X pcw_ttc1_clk2_peripheral_clksrc=CPU_1X
pcw_wdt_peripheral_clksrc=CPU_1X pcw_dci_peripheral_clksrc=DDR PLL pcw_pcap_peripheral_clksrc=IO PLL pcw_usb_reset_polarity=Active Low
pcw_enet_reset_polarity=Active Low pcw_i2c_reset_polarity=Active Low pcw_fpga_fclk0_enable=1 pcw_fpga_fclk1_enable=1
pcw_fpga_fclk2_enable=1 pcw_fpga_fclk3_enable=1 pcw_nor_sram_cs0_t_tr=1 pcw_nor_sram_cs0_t_pc=1
pcw_nor_sram_cs0_t_wp=1 pcw_nor_sram_cs0_t_ceoe=1 pcw_nor_sram_cs0_t_wc=2 pcw_nor_sram_cs0_t_rc=2
pcw_nor_sram_cs0_we_time=0 pcw_nor_sram_cs1_t_tr=1 pcw_nor_sram_cs1_t_pc=1 pcw_nor_sram_cs1_t_wp=1
pcw_nor_sram_cs1_t_ceoe=1 pcw_nor_sram_cs1_t_wc=2 pcw_nor_sram_cs1_t_rc=2 pcw_nor_sram_cs1_we_time=0
pcw_nor_cs0_t_tr=1 pcw_nor_cs0_t_pc=1 pcw_nor_cs0_t_wp=1 pcw_nor_cs0_t_ceoe=1
pcw_nor_cs0_t_wc=2 pcw_nor_cs0_t_rc=2 pcw_nor_cs0_we_time=0 pcw_nor_cs1_t_tr=1
pcw_nor_cs1_t_pc=1 pcw_nor_cs1_t_wp=1 pcw_nor_cs1_t_ceoe=1 pcw_nor_cs1_t_wc=2
pcw_nor_cs1_t_rc=2 pcw_nor_cs1_we_time=0 pcw_nand_cycles_t_rr=1 pcw_nand_cycles_t_ar=1
pcw_nand_cycles_t_clr=1 pcw_nand_cycles_t_wp=1 pcw_nand_cycles_t_rea=1 pcw_nand_cycles_t_wc=2
pcw_nand_cycles_t_rc=2
processing_system7_v5_5_processing_system7/1
iptotal=1 x_ipproduct=Vivado 2015.1 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=processing_system7 x_ipversion=5.5 x_ipcorerevision=1 x_iplanguage=VERILOG
x_ipsimlanguage=MIXED c_en_emio_pjtag=0 c_en_emio_enet0=0 c_en_emio_enet1=0
c_en_emio_trace=0 c_include_trace_buffer=0 c_trace_buffer_fifo_size=128 use_trace_data_edge_detector=0
c_trace_pipeline_width=8 c_trace_buffer_clock_delay=12 c_emio_gpio_width=64 c_include_acp_trans_check=0
c_use_default_acp_user_val=0 c_s_axi_acp_aruser_val=31 c_s_axi_acp_awuser_val=31 c_m_axi_gp0_id_width=12
c_m_axi_gp0_enable_static_remap=0 c_m_axi_gp1_id_width=12 c_m_axi_gp1_enable_static_remap=0 c_s_axi_gp0_id_width=6
c_s_axi_gp1_id_width=6 c_s_axi_acp_id_width=3 c_s_axi_hp0_id_width=6 c_s_axi_hp0_data_width=64
c_s_axi_hp1_id_width=6 c_s_axi_hp1_data_width=64 c_s_axi_hp2_id_width=6 c_s_axi_hp2_data_width=64
c_s_axi_hp3_id_width=6 c_s_axi_hp3_data_width=64 c_m_axi_gp0_thread_id_width=12 c_m_axi_gp1_thread_id_width=12
c_num_f2p_intr_inputs=1 c_irq_f2p_mode=DIRECT c_dq_width=32 c_dqs_width=4
c_dm_width=4 c_mio_primitive=54 c_trace_internal_width=2 c_use_axi_nonsecure=0
c_use_m_axi_gp0=1 c_use_m_axi_gp1=0 c_use_s_axi_gp0=0 c_use_s_axi_hp0=0
c_use_s_axi_hp1=0 c_use_s_axi_hp2=0 c_use_s_axi_hp3=0 c_use_s_axi_acp=0
c_ps7_si_rev=PRODUCTION c_fclk_clk0_buf=true c_fclk_clk1_buf=true c_fclk_clk2_buf=true
c_fclk_clk3_buf=true c_package_name=clg400

report_utilization
slice_logic
slice_luts_used=2896 slice_luts_fixed=0 slice_luts_available=17600 slice_luts_util_percentage=16.45
lut_as_logic_used=2770 lut_as_logic_fixed=0 lut_as_logic_available=17600 lut_as_logic_util_percentage=15.74
lut_as_memory_used=126 lut_as_memory_fixed=0 lut_as_memory_available=6000 lut_as_memory_util_percentage=2.10
lut_as_distributed_ram_used=0 lut_as_distributed_ram_fixed=0 lut_as_shift_register_used=126 lut_as_shift_register_fixed=0
slice_registers_used=3378 slice_registers_fixed=0 slice_registers_available=35200 slice_registers_util_percentage=9.60
register_as_flip_flop_used=3378 register_as_flip_flop_fixed=0 register_as_flip_flop_available=35200 register_as_flip_flop_util_percentage=9.60
register_as_latch_used=0 register_as_latch_fixed=0 register_as_latch_available=35200 register_as_latch_util_percentage=0.00
f7_muxes_used=114 f7_muxes_fixed=0 f7_muxes_available=8800 f7_muxes_util_percentage=1.30
f8_muxes_used=0 f8_muxes_fixed=0 f8_muxes_available=4400 f8_muxes_util_percentage=0.00
slice_used=1179 slice_fixed=0 slice_available=4400 slice_util_percentage=26.80
slicel_used=768 slicel_fixed=0 slicem_used=411 slicem_fixed=0
lut_as_logic_used=2770 lut_as_logic_fixed=0 lut_as_logic_available=17600 lut_as_logic_util_percentage=15.74
using_o5_output_only_used=0 using_o5_output_only_fixed= using_o6_output_only_used=2376 using_o6_output_only_fixed=
using_o5_and_o6_used=394 using_o5_and_o6_fixed= lut_as_memory_used=126 lut_as_memory_fixed=0
lut_as_memory_available=6000 lut_as_memory_util_percentage=2.10 lut_as_distributed_ram_used=0 lut_as_distributed_ram_fixed=0
lut_as_shift_register_used=126 lut_as_shift_register_fixed=0 using_o5_output_only_used=2 using_o5_output_only_fixed=
using_o6_output_only_used=112 using_o6_output_only_fixed= using_o5_and_o6_used=12 using_o5_and_o6_fixed=
lut_flip_flop_pairs_used=3775 lut_flip_flop_pairs_fixed=0 lut_flip_flop_pairs_available=17600 lut_flip_flop_pairs_util_percentage=21.45
fully_used_lut_ff_pairs_used=1885 fully_used_lut_ff_pairs_fixed= lut_ff_pairs_with_unused_lut_used=881 lut_ff_pairs_with_unused_lut_fixed=
lut_ff_pairs_with_unused_flip_flop_used=1009 lut_ff_pairs_with_unused_flip_flop_fixed= unique_control_sets_used=114 minimum_number_of_registers_lost_to_control_set_restriction_used=254(Lost)
memory
block_ram_tile_used=42 block_ram_tile_fixed=0 block_ram_tile_available=60 block_ram_tile_util_percentage=70.00
ramb36_fifo_used=42 ramb36_fifo_fixed=0 ramb36_fifo_available=60 ramb36_fifo_util_percentage=70.00
ramb36e1_only_used=42 ramb18_used=0 ramb18_fixed=0 ramb18_available=120
ramb18_util_percentage=0.00
dsp
dsps_used=0 dsps_fixed=0 dsps_available=80 dsps_util_percentage=0.00
clocking
bufgctrl_used=3 bufgctrl_fixed=0 bufgctrl_available=32 bufgctrl_util_percentage=9.38
bufio_used=0 bufio_fixed=0 bufio_available=8 bufio_util_percentage=0.00
mmcme2_adv_used=0 mmcme2_adv_fixed=0 mmcme2_adv_available=2 mmcme2_adv_util_percentage=0.00
plle2_adv_used=0 plle2_adv_fixed=0 plle2_adv_available=2 plle2_adv_util_percentage=0.00
bufmrce_used=0 bufmrce_fixed=0 bufmrce_available=4 bufmrce_util_percentage=0.00
bufhce_used=0 bufhce_fixed=0 bufhce_available=48 bufhce_util_percentage=0.00
bufr_used=0 bufr_fixed=0 bufr_available=8 bufr_util_percentage=0.00
specific_feature
bscane2_used=0 bscane2_fixed=0 bscane2_available=4 bscane2_util_percentage=0.00
capturee2_used=0 capturee2_fixed=0 capturee2_available=1 capturee2_util_percentage=0.00
dna_port_used=0 dna_port_fixed=0 dna_port_available=1 dna_port_util_percentage=0.00
efuse_usr_used=0 efuse_usr_fixed=0 efuse_usr_available=1 efuse_usr_util_percentage=0.00
frame_ecce2_used=0 frame_ecce2_fixed=0 frame_ecce2_available=1 frame_ecce2_util_percentage=0.00
icape2_used=0 icape2_fixed=0 icape2_available=2 icape2_util_percentage=0.00
startupe2_used=0 startupe2_fixed=0 startupe2_available=1 startupe2_util_percentage=0.00
xadc_used=0 xadc_fixed=0 xadc_available=1 xadc_util_percentage=0.00
primitives
fdre_used=3205 fdre_functional_category=Flop & Latch lut6_used=1368 lut6_functional_category=LUT
lut3_used=760 lut3_functional_category=LUT lut5_used=443 lut5_functional_category=LUT
lut4_used=364 lut4_functional_category=LUT lut2_used=193 lut2_functional_category=LUT
fdse_used=173 fdse_functional_category=Flop & Latch bibuf_used=130 bibuf_functional_category=IO
muxf7_used=114 muxf7_functional_category=MuxFx srlc32e_used=105 srlc32e_functional_category=Distributed Memory
carry4_used=96 carry4_functional_category=CarryLogic obuf_used=51 obuf_functional_category=IO
ramb36e1_used=42 ramb36e1_functional_category=Block Memory lut1_used=36 lut1_functional_category=LUT
srl16e_used=33 srl16e_functional_category=Distributed Memory ibuf_used=18 ibuf_functional_category=IO
obuft_used=13 obuft_functional_category=IO bufg_used=3 bufg_functional_category=Clock
ps7_used=1 ps7_functional_category=Specialized Resource
io_standard
pci33_3=0 lvcmos15=0 lvttl=0 diff_sstl18_ii=0
hstl_i=0 mobile_ddr=0 lvcmos12=0 lvcmos33=1
diff_sstl15=0 hstl_ii=0 diff_mobile_ddr=0 hsul_12=0
lvcmos25=0 lvcmos18=0 hstl_i_18=0 diff_hsul_12=0
hstl_ii_18=0 sstl18_i=0 sstl18_ii=0 sstl15=0
sstl15_r=0 sstl135=0 sstl135_r=0 lvds_25=0
diff_hstl_i=0 rsds_25=0 diff_hstl_ii=0 tmds_33=0
diff_hstl_i_18=0 mini_lvds_25=0 diff_hstl_ii_18=0 ppds_25=0
diff_sstl18_i=0 diff_sstl15_r=0 diff_sstl135=0 diff_sstl135_r=0
blvds_25=0

router
usage
lut=3040 ff=3378 bram36=42 bram18=0
ctrls=114 dsp=0 iob=69 bufg=0
global_clocks=3 pll=0 bufr=0 nets=13427
movable_instances=7488 pins=51587 bogomips=0 high_fanout_nets=6
effort=2 threads=2 router_timing_driven=1 timing_constraints_exist=1
congestion_level=0 estimated_expansions=5788092 actual_expansions=9801221 router_runtime=28.933000

synthesis
command_line_options
-part=xc7z010clg400-2 -name=default::[not_specified] -top=zap_top -include_dirs=default::[not_specified]
-generic=default::[not_specified] -verilog_define=default::[not_specified] -constrset=default::[not_specified] -seu_protect=default::none
-flatten_hierarchy=default::rebuilt -gated_clock_conversion=default::off -directive=default::default -rtl=default::[not_specified]
-link_dcps=default::[not_specified] -rtl_load_constraints=default::[not_specified] -bufg=default::12 -fanout_limit=default::10000
-shreg_min_size=default::3 -mode=default::default -fsm_extraction=default::auto -keep_equivalent_registers=default::[not_specified]
-resource_sharing=default::auto -cascade_dsp=default::auto -control_set_opt_threshold=default::auto
usage
elapsed=00:05:15s memory_peak=927.309MB memory_gain=649.055MB hls_ip=0

xsim
command_line_options
-sim_mode=default::behavioral -sim_type=default::